1. Field of the Invention
This invention relates to interconnect structures for high-speed microprocessors, application specific integrated circuits (ASICs), and other high speed IC""s. The invention provides ultra low dielectric constant (low-k) interconnect structures having enhanced circuit speed, precise values of conductor resistance, and improved mechanical integrity. The structures of this invention have improved toughness and adhesion along with improved control over the metal line resistance compared to conventional structures. The present invention also provides many additional advantages which shall become apparent as described below.
2. Background Art
This application is related to application Ser. No. 09/795,431, entitled Low-k Dielectric Interconnect Structure Comprised of a Multi Layer of Spin-On Porous Dielectrics, assigned to the same assignee as the present application, and filed on Feb. 28, 2001, the contents of which are incorporated herein by reference.
Many low-k dielectric plus copper interconnect structures of the dual damascene type are known. For example, reference is made to U.S. Pat. No. 6,383,920, which is assigned to the same assignee as the present invention, and is incorporated in its entirety by reference, as if fully set forth herein. However, in order to achieve the necessary reduction in the RC delay in the future generations, porous materials must be used as the dielectric. In addition, due to the 5-20 nanometer pore sizes of porous organic materials, a buried etch stop layer is necessary to give smooth metal line bottoms. These structures undergo several processing steps including chemical mechanical polishing (CMP) of the copper, which create stresses within the dielectric stack that can lead to delamination. Delamination can occur due to poor adhesion at the etch stop to dielectric interfaces, or within the dielectric due to decreased toughness of the porous dielectric and increased stress near the interfaces.
It is an object of this invention to provide an ultra low-k dielectric plus copper interconnect structure of the dual damascene type with precise and uniform control over the copper conductor resistance with increased toughness and adhesion to prevent delaminations during CMP.
It is an object of this invention to provide a porous dielectric stack with a buried RIE stop with improved toughness and adhesion that is based on a multilayer of spin coated dielectrics.
It is an object of this invention to provide a low-k dielectric plus copper interconnect structure with precise and uniform control over the copper conductor resistance that is based on a multilayer of spin coated dielectric layers, with improved toughness and adhesion and decreased line roughness.
It is another object of this invention to provide a method for making the inventive structure.
The structures of this invention are unique in that they have an ultra-thin non-porous tough dielectric layer between the porous dielectric and the buried etch stop layer. This tough, thin non-porous dielectric layer serves several purposes: it improves toughness, adhesion and reliability of the interconnect structure. To improve adhesion, the non-porous layer is a version of the porous dielectric with a fracture toughness of greater than 0.3 MPa-m1/2 which will covalently bond with the porous dielectric to create one network, while increasing the surface area of contact with the etch stop layer by eliminating pores at the surface. Increased toughness is achieved by incorporating a tough material near the interface in the area of increased stress in the structure. This type of tough material does not have the necessary properties to support the very small pores required by the porous dielectric and therefore generally cannot be used as the matrix for the porous dielectric. Finally, by incorporating a non-porous dielectric layer between the etch stop layer and the porous dielectric layer, smoother lines can be achieved by eliminating pores at the bottom of the etch stop.
Thus, the present invention is directed to a metal wiring plus porous low dielectric constant (low-k) interconnect structure having improved toughness and adhesion, of the dual damascene type with a spin-on buried RIE stop. The inventive structure is comprised of: a) a multilayer of all spin-on dielectric materials which are applied sequentially in a single tool, and then cured in a single furnace cure step, and b) a plurality of patterned metal conductors within the dielectric multilayer. The improved toughness and adhesion is obtained by incorporating a thin, non-porous dielectric layer, which has a fracture toughness greater than 0.3 MPa-m1/2, between the porous dielectric and the etch stop, between the etch stop and the porous dielectric, or both.
In accordance with the invention, a structure, and in particular an electrical interconnect structure, comprises a substrate; a plurality of porous dielectric layers disposed on the substrate; an etch stop layer disposed between a first of the dielectric layers and a second of the dielectric layers; and at least one thin, non-porous dielectric layer disposed between at least one of the porous dielectric layers and the etch stop layer. The thin, non-porous dielectric layer may have a thickness of substantially 25 to 150 Angstroms. Preferably, the thin, non-porous dielectric layer has a composition with reactive functionalities identical to those of the porous dielectric layers and in particular a composition which forms a covalent bond with the composition of the porous dielectric layers. The thin, non-porous dielectric layer may be comprised of a material selected from the group consisting of SiLK(trademark), GX-3(trademark), or other low k dielectric materials that exhibit fracture toughness values greater than 0.3 MPa-m1/2, preferably greater than 0.35 MPa-m1/2, and will covalently bond to the porous dielectric layer. Materials of this kind are described in Patent Cooperation Treaty International Patent Application WO 00/40637 entitled Low Dielectric Constant Polymers Having Good Adhesion and Toughness and Articles Made With Such Polymers of Edward O. Shaffer II et al. which is assigned to The Dow Chemical Company.
At least one of the porous dielectric layers is comprised of a material selected from the group consisting of porous SiLK(trademark), GX-3p(trademark), or other porous low-k dielectric layers. Materials of this kind are described in Patent Cooperation Treaty International Patent Application WO 00/31183 entitled A composition containing a cross-linkable matrix precursor and a porogen, and a porous matrix prepared therefrom of Kenneth, J. Bruza et al. which is assigned to The Dow Chemical Company, the contents of which are incorporated herein in their entirety by reference. It may have a thickness of substantially 600-5000 Angstroms. In general, at least one of the porous dielectric layers has the same chemical composition as another of the porous dielectric layers. At least one of the porous dielectric layers may be of substantially the same thickness as another of the porous dielectric layers and have a thickness of substantially 600-5000 Angstroms.
The etch stop layer may be comprised of HOSP(trademark), HOSP BESt(trademark), Ensemble(trademark) Etch Stop, Ensemble(trademark) Hard Mask, organo silsesquioxanes, hydrido silsesquioxanes, hydrido-organo silsesquioxanes, siloxanes, or other spin-on material with etch selectivity to the porous dielectric. Materials of this kind are described in U.S. Pat. No. 6,218,020 entitled Dielectric films from organohydridosiloxane resins with high organic content of Nigel P. Hacker et al. which is assigned to AlliedSignal Inc., and U.S. Pat. No. 6,177,199 entitled Dielectric films from organohydridosiloxane resins with low organic content of Nigel P. Hacker et al. which is assigned to AlliedSignal Inc., the contents of which are incorporated herein in their entirety by reference. It may have a thickness of substantially 200-600 Angstroms.
The structure may further comprise a plurality of patterned metal conductors formed within a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers. At least one of the patterned metal conductors may be an electrical via or a line connected to the via.
The invention is also directed to a method for forming an electrical interconnect structure on a substrate, the structure having a plurality of porous dielectric layers disposed on the substrate and an etch stop layer between a first of the dielectric layers and a second of the dielectric layers. The method comprises forming at least one thin, non-porous dielectric layer between at least one of the porous dielectric layers and the etch stop layer. The method further comprising forming a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers, and forming a plurality of patterned metal conductors within the multilayer stack. At least one of the patterned metal conductors may be formed as an electrical via. At least one of the patterned metal conductors may be a line connected to the via.
The multilayer dielectric stack is applied to the substrate by spin coating. The method may further comprise baking the individual layers of the multilayer dielectric stack on a hot plate. The method may further comprise curing the multilayer dielectric stack. The curing of the multiplayer dielectric stack may be accomplished using a furnace in a single step.
The method also includes applying a miltilayer dielectric stack to the substrate and baking the multilayer dielectric stack, so that the applying and baking are accomplished in a single spin-coat tool. Additional dielectric layers may be added, and dual damascene conductors may be formed in the additional layers.
Other and further objects, advantages and features of the present invention will be understood by reference to the following specification in conjunction with the annexed drawings, wherein like parts have been given like numbers.